BITS WILP Reconfigurable Computing Handout 2018-H1

BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

WORK INTEGRATED LEARNING PROGRAMMES

Digital Learning

Part A: Content Design

Course Title	RECONFIGURABLE COMPUTING
Course No(s)	ES ZG554
Credit Units	5
Credit Model	xx
Content Authors	PAWAN SHARMA

Course Objectives

No	Objectives
CO1	To understand various conventional computing platforms and how they are different from reconfigurable platforms
CO2	Introduce Reconfigurable Computing Architecture with emphasis on Field Programmable Gate Array (FPGA)
CO3	Cover design and implementation of digital designs in Reconfigurable hardware using Verilog HDL using Xilinx software
CO4	Introduce reconfigurable computing system synthesis, technology mapping, placement and routing architectures
CO5	Introduce Reconfiguration Management and partial reconfiguration techniques

Text Book(s)

T1	Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications. Christophe Bobda, Springer,  2007

Reference Book(s) & other resources

R1	Wolf Wayne, FPGA Based System Design, Pearson Edu, 2004.
R2	Scott Hauck, André DeHon, Reconfigurable Computing - The Theory and Practice of FPGA Based Computation, The Morgan Kaufmann Series in Systems on Silicon, 2007.
R3	Verilog HDL, Samir Palnitkar, Prentice Hall, 2003.
R4	R Vaidyanathan, Trahan Jerry, Dynamic Reconfiguration: Architectures and Algorithms, L, Kluwer Academic, 2003.
R5	Xilinx,  Altera and Microsemi  Architecture reference manual
R6	Giovanni De Micheli, synthesis and optimization of digital circuits, Tata McGraw-Hill, 2003
R7	R. Druyer, L. Torres, P. Benoit, P. V. Bonzom and P. Le-Quere, "A survey on security features in modern FPGAs," Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015 10th International Symposium on, Bremen, 2015, pp. 1-8. doi: 10.1109/ReCoSoC.2015.7238102 https://www.altera.com/en_US/pdfs/literature/wp/wp-01111-anti-tamper.pdf http://www.xilinx.com/support/documentation/white_papers/wp365_Solving_Security_Concerns.pdf http://www.microsemi.com/document-portal/doc_view/132850-secure-architecture-in-microsemi-fpgas-and-soc-fpgas-an-overview

Content Structure

                   1.      Introduction

                                     1.1.   General Purpose Computing

                                     1.2.   Domain Specific Computing

                                     1.3.   Application Specific Computing

                                     1.4.   Reconfigurable Computing

                   2. Reconfigurable Computing Hardware

                                     2.1.   An overview of programmable logic

                                                        2.1.1.   PLA

                                                        2.1.2.   PAL

                                                        2.1.3.   SPLD

                                                        2.1.4.   CPLD

                   3.      Hardware Description Languages and Logic Design

                                     3.1.   Modeling with HDLs

                                                        3.1.1.   Verilog

                                     3.2.   Combinational Network Delay,

                                     3.3.   Power and Energy Optimization

                   4.Reconfigurable Computing Architecture

                                     4.1.   FPGA Architecture, FPGA Fabrics

                                                        4.1.1.   SRAM Based-FPGAs

                                                        4.1.2.   Permanently Programmed FPGAs

                                                        4.1.3.   Programmable I/O,

                                     4.2.   Circuit Design of FPGA Fabrics,

                                     4.3.   Architecture of FPGA Fabrics, Case Studies, Xilinx

                                     4.4.   Fine - Grained and Course - Grained Reconfigurable Architecture

                   5.      Programming Reconfigurable Systems

                                     5.1.   Logic Design Process

                                                        5.1.1.   Design

                                                        5.1.2.   Integration

                                                        5.1.3.   FPGA Design Flow

                                     5.2.   Implementation Approaches

                                                        5.2.1.   Run Time Reconfiguration (RTR)

                                                        5.2.2.   Partial Reconfiguration (PR)

                   6.      Mapping Designs to Reconfigurable Platform

                                     6.1.   Logic Implementation for FPGAs,

                                     6.2.   Syntax-Directed Translation

                                     6.3.   Logic Synthesis

                                                        6.3.1.   Two-Level Logic Synthesis

                                                        6.3.2.   Multi-Level Logic Synthesis

                                                        6.3.3.   Technology Mapping

                                                        6.3.4.   LUT-Based Technology Mapping

                   7.      High-Level Synthesis for Reconfigurable Devices

                                     7.1.   Modeling

                                                        7.1.1.   DFG, CFG

                                     7.2.   Introduction to Binding, Scheduling and Allocation, Temporal Partitioning

                                     7.3.   Temporal Partitioning Algorithms

                                                        7.3.1.   ASAP

                                                        7.3.2.   ALAP

                                                        7.3.3.   List Scheduling

                                                        7.3.4.   Integer Linear Programming

                   8.      Temporal Placement and Routing

                                     8.1.   Offline and Online Temporal Placement

                                     8.2.   Routing Cost, Routing-Conscious Placement

                   9.      Online Communication

                                     9.1.   Communication at run-time  between modules on the Reconfigurable Device

               10.      Reconfiguration Management

                                  10.1.   Configuration Architectures

                                                    10.1.1.   Single Context

                                                    10.1.2.   Multi-Context FPGAs

                                                    10.1.3.    Introduction to Partial Reconfiguration

                                                    10.1.4.   Pipeline and Block Reconfigurable

                                  10.2.   Managing the Reconfiguration Process

                                                    10.2.1.   Configuration Grouping, Caching and Scheduling

                                                    10.2.2.   Relocation and Defragmentation

                                                    10.2.3.   Contest Switching

                                  10.3.   Reducing configuration Transfer Time

                                                    10.3.1.   Architectural Approach

                                                    10.3.2.   Configuration Compression

                                                    10.3.3.   Configuration Data Reuse

Learning Outcomes:

No	Learning Outcomes. Knowledge in the following areas
LO1	Understand various computing platform, Reconfigurable computing architectures
LO2	Understand the flow of reconfigurable system design and implementation on hardware
LO3	Synthesize Reconfigurable system
LO4	Understand Reconfiguration management

Part B: Learning Plan

Academic Term	Second   Semester 2017-2018
Course Title	RECONFIGURABLE COMPUTING
Course No	ES ZG554
Lead Instructor	Pawan Sharma

Contact Hour 1

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH		General purpose processor architecture
During CH	T1 Ch 1	General Purpose Computing, Domain Specific Computing, Application Specific Computing
Post CH

Contact Hour 2

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH		Basics of digital design, Boolean logic minimization, K-map
During CH	T1 Ch1	Reconfigurable Computing, Fields of application
Post CH

Contact Hour 3

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH		Digital gates, Boolean logic, Decoder, MUX, flip flop, latches
During CH	T1 Ch2	An overview of programmable logic, ROM, PLA, PAL
Post CH

Contact Hour 4

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	R3	SPLD, CPLD
Post CH

Contact Hour 5

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH		Digital design macro logic blocks
During CH	R3	Modeling with HDLs, Verilog/VHDL
Post CH

Contact Hour 6

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	R1	Combinational Network Delay, Power and Energy Optimization
Post CH

Contact Hour 7

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch2 R1 Ch3	FPGA Architecture, SRAM Based-FPGAs, Anti-fuse FPGAs
Post CH

Contact Hour 8

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch2 R1 Ch3	FPGA Structure, Programmable IO
Post CH

Contact Hour 9

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	R1 Ch3	Circuit Design of FPGA Fabrics
Post CH

Contact Hour 10

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	R5	Architecture of FPGA Fabrics, Case Studies, Xilinx
Post CH

Contact Hour 11

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch2	Fine - Grained and Course - Grained Reconfigurable Architecture, Hybrid FPGAs
Post CH

Contact Hour 12

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch3	Logic Design Process, Design and Integration
Post CH

Contact Hour 13

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch3	FPGA Design Flow
Post CH

Contact Hour 14

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch3	Implementation Approaches Run Time Reconfiguration (RTR) )
Post CH

Contact Hour 15

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch3	Partial Reconfiguration (PR
Post CH

Contact Hour 16

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	R1 Ch4	Logic Implementation for FPGAs, Syntax-Directed Translation
Post CH

Contact Hour 17

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	R1 Ch4 R6	Two-Level Logic Synthesis Multi-Level Logic Synthesis
Post CH

Contact Hour 18

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	R1 Ch4 R6 Ch8	Node representation, node manipulation
Post CH

Contact Hour 19

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	R6 Ch10	Technology Mapping for custom logic
Post CH

Contact Hour 20

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch3	LUT-Based Technology Mapping Chortle algorithm
Post CH

Contact Hour 21

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch3	LUT-Based Technology Mapping Chortle crf algorithm
Post CH

Contact Hour 22

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch3	LUT-Based Technology Mapping FlowMap algorithm
Post CH

Contact Hour 23

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch4	High-Level Synthesis for Reconfigurable Devices Modeling, DFG, CFG
Post CH

Contact Hour 24

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch4	Introduction to Binding, Scheduling and Allocation
Post CH

Contact Hour 25

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch4	Temporal Partitioning, Temporal Partitioning Algorithms, ASAP, ALAP
Post CH

Contact Hour 26

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch4	List Scheduling
Post CH

Contact Hour 27

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch4	Integer Linear Programming
Post CH

Contact Hour 28

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch5	Offline and Online Temporal Placement
Post CH

Contact Hour 29

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch5	Routing Cost, Routing-Conscious Placement
Post CH

Contact Hour 30

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	T1 Ch 6	Communication at run-time  between modules on the Reconfigurable Device (only introduction)
Post CH

Contact Hour 31

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	R2 Ch4	Configuration Architectures Single Context, Multi-Context FPGAs,  Introduction to Partial Reconfiguration, Pipeline and Block Reconfigurable
Post CH

Contact Hour 32

Type	Content Ref.	Topic Title	Study/HW Resource Reference
Pre CH
During CH	R2 Ch4	Managing the Reconfiguration Process Configuration Grouping, Caching and Scheduling Relocation and Defragmentation Contest Switching Reducing configuration Transfer Time Architectural Approach Configuration Compression Configuration Data Reuse
Post CH

Laboratory Details: The Course would involve use of Xilinx Vivado software and Z-board for carrying out the graded assignments. The software may be accessed using the online lab resources provided by BITS, Pilani. The details would be shared during the contact hours.

Evaluation Scheme:  

Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session

No	Name	Type	Duration	Weight	Day, Date, Session, Time
EC-1	Assignment-I	Online	-	10%	February 1 to 10, 2018
	Assignment-II	Online	-	10%	March 1 to 10, 2018
EC-2	Mid-Semester Test	Closed Book	2 hours	30%	04/03/2018 (FN)   10 AM – 12 Noon
EC-3	Comprehensive Exam	Open Book	3 hours	50%	22/04/2018 (FN) 9 AM – 12 Noon

 Syllabus for Mid-Semester Test (Closed Book): Topics in Session Nos. 1 to 15

Syllabus for Comprehensive Exam (Open Book): All topics (Session Nos. 1 to 32)

Important links and information:

Elearn portal: https://elearn.bits-pilani.ac.in

Students are expected to visit the Elearn portal on a regular basis and stay up to date with the latest announcements and deadlines.

Contact sessions: Students should attend the online lectures as per the schedule provided on the Elearn portal.

Evaluation Guidelines:

1.       EC-1 consists of either two Assignments. Students will attempt them through the course pages on the Elearn portal. Announcements will be made on the portal, in a timely manner.

2.       For Closed Book tests: No books or reference material of any kind will be permitted.

3.       For Open Book exams: Use of books and any printed / written reference material (filed or bound) is permitted. However, loose sheets of paper will not be allowed. Use of calculators is permitted in all exams. Laptops/Mobiles of any kind are not allowed. Exchange of any material is not allowed.

4.       If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the student should follow the procedure to apply for the Make-Up Test/Exam which will be made available on the Elearn portal. The Make-Up Test/Exam will be conducted only at selected exam centres on the dates to be announced later.

It shall be the responsibility of the individual student to be regular in maintaining the self study schedule as given in the course handout, attend the online lectures, and take all the prescribed evaluation components such as Assignment/Quiz, Mid-Semester Test and Comprehensive Exam according to the evaluation scheme provided in the handout.